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RT9032 ? ds9032-03 august 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. applications mobile phone smart hand-held devices digital still camera battery-powered equipments pcmcia cards programmable dual output linear regulator ordering information marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. general description the RT9032 is a dual channels, low noise and low dropout voltage regulator souring up to 300ma at each channel. the output voltage range is from 1.1v to 3.3v by operating voltage range from 2.5v to 5.5v. the output voltages of the RT9032 can be programmed by setting the voltage of p1 and p2. there are 9 different voltage settings in one chip. user can choose output voltages easily by setting p1, p2 to vdd, gnd or floating. the RT9032 offers 3% accuracy, low dropout (330mv @300ma) and extremely low ground current, only 32 a per ldo. the shutdown current is near to zero current which is suitable for battery-powered device. other features include current limiting, over temperature protection and output short circuit protection. the RT9032 can operate stable with very small ceramic output capacitors, reducing required board space and component cost. the RT9032 is available in wdfn-8l 2x2 and wqfn-8l 1.6x1.6 (col) packages. features wide operating voltage ranges : 2.5v to 5.5v dual ldo output pin programmable output voltage low-noise for rf application no noise bypass capacitor required fast response in line/load transient low quiescent current of 32 a/ldo 3% high output accuracy current limiting protection thermal shutdown protection short circuit protection tiny wdfn-8l 2x2 and wqfn-8l 1.6x1.6 (col) packages rohs compliant and halogen free note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) wdfn-8l 2x2 wqfn-8l 1.6x1.6 (col) vin en1 vout1 vout2 p2 en2 7 6 5 1 2 3 p1 gnd 4 8 vin en1 vout1 vout2 gnd p2 7 6 5 1 2 3 4 8 p1 en2 g n d 9 RT9032 package type qw : wdfn-8l 2x2 (w-type) qwa : wqfn-8l 1.6x1.6 (col) (w-type) lead plating system g : green (halogen free and pb free) output voltage a : combination a b : combination b c : combination c d : combination d j : combination j
RT9032 2 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit p1 state p2 state vout1 vout2 l l 1.5v 2.8v l h 1.8v 2.9v l open 1.8v 2.8v h l 1.8v 2.7v h h 1.8v 2.6v h open 2.7v 2.8v open l 2.8v 2.8v open h 2.9v 2.9v open open 2.8v 3.3v table for programmable output voltage setting combination a (RT9032a) p1 state p2 state vout1 vout2 l l 1.2v 2.8v l h 1.5v 1.8v l open 1.5v 2.8v h l 1.8v 2.6v h h 1.8v 2.8v h open 2.8v 2.8v open l 2.8v 3.3v open h 3v 3.3v open open 3.3v 3.3v combination b (RT9032b) p1 state p2 state vout1 vout2 l l 1.8v 2.8v l h 1.8v 2.85v l open 1.8v 3v h l 1.85v 2.85v h h 2.6v 2.7v h open 2.6v 3.3v open l 2.85v 3.3v open h 3v 3.3v open open 3.3v 3.3v combination c (RT9032c) p1 state p2 state vout1 vout2 l l 1.8v 2.9v l h 2.6v 2.8v l open 1.8v 2.8v h l 2.9v 2.9v h h 2.8v 3.3v h open 2.8v 2.8v open l 1.8v 2.6v open h 1.8v 2.7v open open 1.5v 2.8v combination d (RT9032d) en1 en2 vout2 vout1 RT9032 gnd vin 1f v in chip enable c in 1f v out1 c out1 1f v out2 c out2 p1 p2
RT9032 3 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. p1 sta te p2 state vou t1 vout2 l l 3.3v 3.3v l h 1.1v 3.3v l open 1.2v 2.5v h l 1.8v 3.3v h h 1.1v 1.8v h open 1.1v 2.5v open l 1.2v 1.8v open h 1.2v 3.3v open open 1.8v 2.5v combination j (RT9032j) functional pin description pin number wdfn 2x2 wqfn 1.6x1.6 (col) pin name pin function 1 1 vin supply input. 2 2 en1 channel 1 enable control.(active high) 3 6 p2 programming input 2. the state of p2 selects one of nine output voltage options. 4 4 p1 programming input 1. the state of p1 selects one of nine output voltage options. 5 3 en2 channel 2 enable control.(active high) 6, 9 (exposed pad) 5 gnd common ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 7 7 vout2 channel 2 output voltage. 8 8 vout1 channel 1 output voltage.
RT9032 4 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram en1 vout1 shutdown and logic control vin v ref current-limit and thermal protection mos driver + - error amplifier vout2 p1 p2 programmable output en2 shutdown and logic control vin v ref current-limit and thermal protection mos driver + - error amplifier p1 p2 programmable output por control vin 0.1a 0.1a
RT9032 5 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) supply input v oltage (vin) ---------------------------------------------------------------------------------------------- 6.5v i/o pin voltage (en1, en2, p1, p2, vout1, vout2) ----------------------------------------------------------- 6.5v power dissipation, p d @ t a = 25 c wdfn-8l 2x2 -------------------------------------------------------------------------------------------------------------- 0.606w wqfn-8l 1.6x1.6 (col) ------------------------------------------------------------------------------------------------ 0.571w package thermal resistance (note 2) wdfn-8l 2x2, ja --------------------------------------------------------------------------------------------------------- 165 c/w wdfn-8l 2x2, jc --------------------------------------------------------------------------------------------------------- 20 c/w wqfn-8l 1.6x1.6 (col), ja ------------------------------------------------------------------------------------------- 175 c/w lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c junction temperature ----------------------------------------------------------------------------------------------------- 150 c storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine model) ----------------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) supply input v oltage ------------------------------------------------------------------------------------------------------ 2.5v to 5.5v junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics parameter symbol test conditions min typ max unit quiescent current (note5) i q v en > 1.5v, -- 65 80 a shutdown current i shdn v en < 0.4v -- -- 1 a output (vout1, vout2) output voltage range v out 1.1 -- 3.3 v dropout voltage (note 6) v drop i out = 300ma -- 330 500 mv output accuracy v i out = 1ma ? 3 -- +3 % line regulation v li ne v in = 2.5v to 5.5v -- -- 0.2 %/v load regulation v lo ad 1ma < i out < 300ma -- -- 0.6 % f = 100hz, i lo ad = 10ma -- 65 -- f = 1khz, i load = 10ma -- 60 -- f = 10khz, i lo ad = 10ma -- 50 -- db f = 100hz, i lo ad = 150ma -- 65 -- f = 1khz, i load = 150ma -- 50 -- power supply rejection rate psrr f = 10khz, i lo ad = 150ma -- 50 -- db (v in = v outx + 0.7v, v enx = v in , c in = c out1 = c out2 =1 f, t a = 25 c unless otherwise specified.)
RT9032 6 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a low effective thermal conductivity single-layer test board per jedec 51-3. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. quiescent, or ground current, is the difference between input and output currents. it is defined by i q = i in - i out under no load condition (i out = 0ma). the total current drawn from the supply is the sum of the load current plus the ground pin current. note 6. the dropout voltage is defined as v in -v out , which is measured when v out is v out(normal) - 100mv. note 7. output voltage vout1/vout2 are configured by p1/p2 state when en1 or en2 go high. subsequent changes to p1/p2 do not change vout1/vout2 unless power on reset by vin or both of en1 and en2. parameter symbol test conditions min typ max unit output voltage discharge resistance in shutdown v in = 5v, en1 = en2 = gnd -- 20 -- output voltage temperature coefficient -- 100 -- ppm/ c enable pin input (en1, en2) logic-high v ih v in = 2.5v to 5.5v, power on 1.5 -- -- en threshold voltage logic-low v il v in = 2.5v to 5.5v, shutdown -- -- 0.4 v tri-state input (p1, p2) v in = 2.5v to 5.5v hi, lo state -- -- 1k p1/p2 termination resistance from input to vdd or gnd for setting hi, lo, open states (note 7) v in = 2.5v to 5.5v open state 100k -- -- decision time td open pin with input loading 50pf (including pad & pcb trace) -- -- 20 s protection current limit i lim r load = 1 330 430 600 ma thermal shutdown temperature t sd -- 170 -- thermal shutdown hysteresis t sd -- 30 -- c
RT9032 7 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics v out1 = 1.8v, v out2 = 2.8v, i out1 = i out2 = 10ma line transient response v in (v) time (100 s/div) v out2 (20mv/div) 4.8 3.8 v out1 (20mv/div) dropout voltage vs. load current 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 load current (ma) dropout voltage (mv) v out = 2.8v 125 c 25 c -40 c v out1 = 1.8v, v out2 = 2.8v, i out1 = i out2 = 1ma line transient response v in (v) time (100 s/div) v out2 (20mv/div) 4.8 3.8 v out1 (20mv/div) quiescent current vs. temperature 0 10 20 30 40 50 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) quiescent current ( a) v in = 4.3v output voltage vs. temperature 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) output voltage (v) v in = 4.3v, no load output voltage vs. temperature 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) output voltage (v) v in = 4.3v, no load
RT9032 8 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power off from en time (25 s/div) v out2 (1v/div) v out1 (1v/div) en (5v/div) v in = 5v, v out1 = 1.8v, v out2 = 2.8v, i out1 = i out2 = 50ma power on from en time (25 s/div) v out2 (1v/div) v out1 (1v/div) en (5v/div) v in = 5v, v out1 = 1.8v, v out2 = 2.8v, i out1 = i out2 = 50ma i out1 = i out2 = 10ma to 100ma load transient response time (250 s/div) v out2 (20mv/div) v out1 (20mv/div) i out (100ma/div) v in = 4.3v, v out1 = 1.8v, v out2 = 2.8v i out1 = i out2 = 10ma to 50ma load transient response time (250 s/div) v out2 (20mv/div) v out1 (20mv/div) i out (50ma/div) v in = 4.3v, v out1 = 1.8v, v out2 = 2.8v v out1 = 1.8v, v out2 = 2.8v, i out1 = i out2 = 100ma line transient response v in (v) time (100 s/div) v out2 (10mv/div) 4.8 3.8 v out1 (10mv/div) v out1 = 1.8v, v out2 = 2.8v, i out1 = i out2 = 50ma line transient response v in (v) time (100 s/div) v out2 (20mv/div) 4.8 3.8 v out1 (20mv/div)
RT9032 9 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vout2 psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 1000000 frequency (hz) psrr (db) v in = v en = 4.3v 50mv, v out = 2.8v, i out = 50ma i out = 10ma i out = 150ma vout1 psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 1000000 frequency (hz) psrr(db) v in = v en = 4.3v 50mv, v out = 1.8v, i out = 50ma i out = 10ma i out = 150ma noise time (10ms/div) v out (100uv/div) v in = v en = 5v, i out = 50ma noise time (10ms/div) v out (100uv/div) v in = v en = 5v, no load
RT9032 10 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information like any low-dropout regulator, the external capacitors used with the RT9032 must be carefully selected for regulator stability and performance. using a capacitor whose value is > 1 f on the RT9032 input and the amount of capacitance can be increased without limit. the input capacitor must be located at a distance of not more than 0.5 inch from the input pin of the ic and returned to a clean analog ground. any good quality ceramic or tantalum can be used for this capacitor. the capacitor with larger value and lower esr (equivalent series resistance) provides better psrr and line-transient response. the output capacitor must meet both requirements for minimum amount of capacitance and esr in all ldos application. the RT9032 is designed specifically to work with low esr ceramic output capacitor for space-saving and performance consideration. using a ceramic capacitor whose value is at least 1 f with esr is > 20m on the RT9032 output ensures stability. the RT9032 still works well with output capacitor of other types due to the wide stable esr range. figure 1 shows the curves of allowable esr range as a function of load current for various output capacitor values. output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and psrr. the output capacitor should be located at not more than 0.5 inch from the output pin of the RT9032 and returned to a clean analog ground. en the RT9032 goes into shutdown mode when the en pin is in a logic low condition. during this condition, the pass transistor, error amplifier, and band gap are turned off, reducing the supply current to be lower than 1ua. the en pin can be directly tied to vin to keep the part on. programmable output voltage setting there are nine sets of the vout1 and vout2 output voltages that can be achieved by setting three states (high/ low/open) at the p1 and p2 pins. the output voltage setting can be achieved by the preset of p1 and p2 states before vin power on. however, if the p1 and p2 states are changed at the condition that only one of the en pin is turned off-on, the vout1 and vout2 voltages will not be changed. the output voltage can be reset by turning off-on the input power (vin) or both of en pins (en1 = en2). for the output voltage setting please refer to the ? table for programmable output voltage setting ? in page 2. current limit the RT9032 contains an independent current limiter, which monitors and controls the pass transistor ? s gate voltage, limiting the output current to 430ma (typ.). the output can be shorted to ground indefinitely without damaging the part. thermal shutdown protection as the die temperature is >170 c, the chip will enter protection mode. the power mosfet will be turned-off during the protection mode to prevent abnormal operation. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature . the power dissipation definition in device is : p d = (v in ? v out ) x i out + v in x i q figure 1 0.001 0.01 0.1 1 10 100 0 50 100 150 200 250 300 load current(ma) region of stable c out esr( ? ) unstable range stable range v in = 5v, c in = c out1 = c out1 = 1 f/x7r unstable range
RT9032 11 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout considerations careful pcb layout is necessary for better performance. the following guidelines should be followed for good pcb layout. ` place the input and output capacitors as close as possible to the ic. ` keep vin, vout1 and vout2 traces as possible as short and wide. ` connect gnd pin and exposed pad to a large pcb ground plane for maximum thermal dissipation. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ( ja is layout dependent) for wdfn-8l 2x2 is 165 c/w and wqfn-8l 1.6x1.6 (col) is 175 c/w on the standard jedec 51-3 single-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (165 c/w) = 0.606w for wdfn-8l 2x2 packages p d(max) = (125 c ? 25 c) / (175 c/w) = 0.571w for wqfn-8l 1.6x1.6 (col) packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . the figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. figure 3. layout considerations for wdfn-8l 2x2 packages figure 4. layout considerations for wqfn-8l 1.6x1.6 (col) packages figure 2. derating curve of maximum power dissipation 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 153045607590105120135 ambient temperature (c) power dissipation (w) single layer pcb wdfn-8l 2x2 wqfn-8l 1.6x1.6 c in should be placed as close as possible to vin pin for good filtering. c out1 & c out2 should be placed as close as possible to output pin for good filtering. vin en1 vout1 vout2 p2 en2 7 6 5 1 2 3 p1 gnd 4 8 c in c out1 c out2 gnd c out1 c out2 c in c in should be placed as close as possible to vin pin for good filtering. c out1 & c out2 should be placed as close as possible to vout pin for good filtering. the exposed pad should be connected to a strong ground plane for heat sinking and noise reduction. vin en1 vout1 vout2 gnd p2 7 6 5 1 2 3 4 8 p1 en2 g n d 9
RT9032 12 ds9032-03 august 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension w-type 8l dfn 2x2 package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 1.950 2.050 0.077 0.081 d2 1.000 1.250 0.039 0.049 e 1.950 2.050 0.077 0.081 e2 0.400 0.650 0.016 0.026 e 0.500 0.020 l 0.300 0.400 0.012 0.016 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
RT9032 13 ds9032-03 august 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. symbol dimensions in millimeters dimensions in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 1.550 1.650 0.061 0.065 e 1.550 1.650 0.061 0.065 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 8l qfn 1.6x1.6 (col) package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options

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